This invention relates to electronic circuits of the types known as delay lock loops and phase lock loops.
Delay lock loop and phase lock loop circuits may be used to produce a clock signal which has a particular time shift relative to a reference clock signal. Although the clock signal produced by the loop circuit can be delayed relative to the reference clock, a common need is for a clock signal that is advanced relative to the reference clock. Thus, for convenience herein, all signals produced by a loop circuit will be referred to as "advanced clock signals", whether the signal is advanced or delayed relative to the reference clock.
An illustrative situation in which there may be a need for an advanced clock signal occurs in relatively large integrated circuit ("IC") devices such as programmable logic arrays. The reference clock signal may be applied to one input pin of the IC for distribution throughout the device. By the time the reference clock signal reaches portions of the IC that are relatively remote from the input pin, the signal may be significantly delayed (due to signal transmission delay in the IC) relative to the reference clock signal adjacent to the input pin. This can make it difficult to maintain synchronization between the various portions of the IC, and it may necessitate operating the IC at a slower clock rate than would otherwise be possible.
In order to compensate for this problem, a delay lock loop circuit or a phase lock loop circuit may be included on the IC. (For convenience herein, both of these types of circuits are referred to generically as "loop circuits".) The loop circuit is typically located near the reference clock input pin. The loop circuit receives the reference clock signal and produces an advanced clock signal. The advanced clock signal is generally similar to the reference clock signal, except that it is advanced in time relative to the reference clock by an amount which is approximately equal to the time required for a clock signal to travel from portions of the IC that are relatively close to the reference clock input pin to more remote portions of the IC. The advanced clock signal is transmitted to the above-mentioned more remote portions of the IC in lieu of the original reference clock signal, while the reference clock signal continues to be used near the reference clock input pin. In this way all portions of the IC receive synchronized clock signals, which facilitates synchronized operation of the IC, even at very high clock speeds.
The typical loop circuit 10 (see FIG. 1) has a phase frequency detector ("PFD") 12 for comparing the relative phases and frequencies of the reference clock signal 11 and a clock signal 21 that the loop circuit feeds back to the PFD. If the phase of the feed-back clock signal is behind the phase of the reference clock signal, the PFD produces a first type of output signal 13a. If the phase of the feed-back clock signal is ahead of the phase of the reference clock signal, the PFD produces a second type of output signal 13b. The first and second output signals of the PFD may be applied to a charge pump circuit 14, which charges or discharges the charge-storing element of a low-pass filter 16, depending on whether the PFD is producing the first or second output signal. The output signal of the low-pass filter may be applied as a control signal to a variable delay circuit or voltage controlled oscillator ("VCO") 18. If a variable delay circuit is used, the loop circuit is typically called a delay lock loop, and phase frequency detector 12 typically detects phase error (although it could alternatively additionally detect frequency error). The signal applied to the variable delay circuit for delay may be the reference clock signal 11a. If a VCO is used, the loop circuit is typically called a phase lock loop, and phase frequency detector 12 typically detects phase and frequency error. The output signal of the variable delay circuit or the VCO may be the advanced clock signal 19, i.e., the ultimately desired output of the loop circuit. This signal may also be applied to a fixed delay circuit 20, which simulates the clock signal transmission delay that the advanced clock signal is intended to compensate for. The output signal of the fixed delay circuit is the feed-back clock signal 21 applied to the PFD.
The loop circuit is typically arranged so that if the feed-back clock signal is behind or later in time than the reference clock signal, the delay of the variable delay circuit is lessened somewhat (or the frequency of the VCO is increased somewhat) until the phases of the signals applied to the PFD match one another. Conversely, if the feed-back clock signal is ahead of or earlier in time than the reference clock signal, the delay of the variable delay circuit is increased somewhat (or the frequency of the VCO is decreased somewhat) until the phases of the signals applied to the PFD match one another.
Particularly in the case of delay lock loop circuits, it will be noted that the amount of delay required from the variable delay circuit depends on the frequency of the reference clock signal. This is so because each feed-back clock signal transition that the PFD compares to a reference clock signal transition is derived from an earlier reference clock signal transition.
The usefulness of a loop circuit can be increased (thereby increasing the usefulness of the circuitry employing the loop circuit) by increasing the reference clock signal frequency range that the loop circuit can automatically adapt to. For example, it may be desirable to provide a loop circuit that can automatically adapt to reference clock signal frequencies in the range from about 30 to about 70 MHZ. A loop circuit should also not be unduly perturbed or misled by occasional noise or "glitches" in the reference clock signal, either while the loop circuit is attempting to lock on to the reference clock signal or during subsequent normal operation of the loop circuit.
In view of the foregoing, it is an object of this invention to provide improved circuitry and methods for control and operation of loop circuits.
It is a more particular object of this invention to provide improved circuitry and methods for controlling the low-pass filters that are typically included in loop circuits.